1. Field of the Invention
The present invention relates to semiconductor fabrication, and in particular to methods for capping copper interconnects in semiconductor devices.
2. Description of the Related Art
Conventional semiconductor devices comprise conductive interconnects to establish electric contact with conductive structures inside semiconductor substrates. Interconnects comprise metal lines and metal plugs formed in dielectric layers for horizontal and vertical connections.
High performance semiconductor applications require rapid speed in semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature size and space become smaller, the integrated circuit speed becomes more dependent upon the interconnect pattern, and thus, materials utilized in interconnect structures have become a major concern.
One approach to increase the control speed of semiconductor circuitry is to reduce the resistance of interconnects. Cu and Cu alloys are utilized as a better material for replacing Al in VLSI interconnect metallization. Cu exhibits superior electromigration properties and has a lower resistivity than Al. In addition, copper or copper alloy interconnects can be formed by electroless plating and electroplating, which is low cost, has high throughput, high quality, is highly efficient and has good filling capabilities.
Although Cu or Cu alloy interconnects have superior properties for applications, there are drawbacks in Cu implementation. For example, Cu readily diffuses into dielectric layers, particularly silicon dioxide, which results in electrical shorts.
A well-known solution to prevent Cu diffusion is to form diffusion barrier layers between Cu or Cu alloy interconnects and dielectric layers. Conventional diffusion barrier layers include tantalum (Ta)/tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten (W)/tungsten nitride (WN) for encapsulating Cu interconnects. The diffusion barrier layers are usually deposited on bottoms and sidewalls of damascene openings by sputtering before Cu filling. The surface of exposed Cu or Cu alloy interconnects after planarization are conventionally capped by silicon nitride.
The drawback of silicon nitride is poor adhesion to copper. The subsequent process usually causes silicon nitride to peel away from the copper plugs. The peeled silicon nitride creates a path for copper to diffuse outward and for moisture or contaminates to diffuse inward and thus degrade reliability of the interconnects.
In U.S. Pat. No. 5,447,887, the adhesion problem of a silicon nitride capping layer to a copper interconnect is addressed by initially treating the exposed surface with silane in the absence o fa plasma to form a thin layer of copper silicide, and depositing a silicon nitride capping layer thereon.
U.S. Pat. No. 6,492,266 discloses enhancing the adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper silicide layer thereon; or (b) with an ammonia plasma followed by reaction with silane or dichlorosilane to form a copper silicide layer thereon.
U.S. Pat. No. 6,339,025 discloses fabricating a copper capping layer by forming a silicon rich nitride layer on an exposed copper layer. The silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer.